1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the simulation of systems including a processor core and a plurality of hardware devices.
2. Description of the Prior Art
The ability to effectively and efficiently test and/or validate designs is becoming increasingly important. Typical data processing system designs are rapidly increasing in complexity and furthermore are including circuit blocks designed by a variety of different sources or companies. So called system-on-chip (SoC) designs that integrate a large number of functional elements on a single integrated circuit have strong advantages in terms of cost and performance, but require significant amounts of validation and testing before the designs can be reliably released for manufacture. This validation and testing requirement is becoming a bottleneck in getting new systems into the market place. Consequently, measures that can improve the efficiency and effectiveness of such validation and testing of designs are strongly advantageous.
There are currently 3 approaches that can be used to validate a SoC design:    (a) Build a software model of the design and run the same software when the hardware is complete. The problems here include that the hardware models are not fully represented in software in that there is no hardware feedback loop such that different hardware block models can interact fully.    (b) Build VHDL and/or Verilog (trickboxes) models to plug into the external interfaces of the SoC blocks to provide external stimulus to the SoC. This approach is commonly used but suffers from the problem that the code is not very re-usable, and a large amount of knowledge is required of the operation of each trickbox to create effective tests.    (c) Build models of each of the blocks (eVCs) in the SoC using an HVL (hardware verification language) such a Specman to replace existing hardware blocks in turn, such that the modelled blocks can provide stimulus into the system. Here a problem is that the integrity of the system is compromised as existing blocks need to be removed and re-inserted per test.
The copending U.S. patent application U.S. Ser. No. 09/994,023 filed on 27 Nov. 2001 with the same inventor and Assignee as the current application describes a mechanism for the coordinated validation of hardware devices. The disclosure of this earlier copending application is incorporated herein in its entirety by reference.
The copending U.S. patent application entitled “Software and Hardware Simulation” filed on 22 Feb. 2002 describes a mechanism for testing software drivers and their associated hardware. The disclosure of this earlier copending application is incorporated herein in its entirety by reference.